本标准正式规定了卡滞故障模型的各个方面，因为它们与数字电路测试模式的生成有关。其范围包括a）故障计数，b）故障分类，以及c）针对单卡故障模型跨不同自动测试模式生成（ATPG）工具的故障覆盖率报告。故障分级和模拟仅限于数字电路的Verilog门级表示。根据本标准，所有ATPG工具（符合本标准）都有义务以统一的方式报告故障覆盖率。 这有助于为具有不同内核和模块的大型芯片生成统一的覆盖率（以及测试质量）指标，对于这些芯片，测试模式已使用ATPG工具独立生成，或已在外部提供，并已使用ATPG工具模拟，以确定故障覆盖率。

This standard formalizes aspects of the stuck-at fault model as they are relevant to the generation of test patterns for digital circuits. Its scope includes a) fault counting, b) fault classification, and c) fault coverage reporting across different automatic test pattern generation (ATPG) tools, for the single stuck-at fault model. Fault grading and simulation is limited to the Verilog gate level representation of a digital circuit. With this standard, it shall be incumbent on all ATPG tools (that comply with this standard) to report fault coverage in a uniform way. This can facilitate the generation of a uniform coverage (and hence a test quality) metric for large chips with different cores and modules, for which test patterns have been independently generated using an ATPG tool, or have been supplied externally and have been simulated using an ATPG tool to ascertain the fault coverage.