VSB总线的设计是为了满足基于高性能32位微处理器的多处理器系统的需求，该微处理器由板组件构成。它包括一个高速异步数据传输总线，允许主设备根据4种周期（仅地址、单次传输、块传输和中断确认周期）指导二进制数据与从设备之间的传输。它还包括仲裁总线，使仲裁器模块和/或请求器模块能够根据两种仲裁方法（串联或并联）协调数据传输总线的使用。 注:关于本出版物的价格，请参考ISO/IEC价格代码表。

The VSB bus was designed to meet the needs of multiprocessor systems based on high-performance 32-bit microprocessors built up from board assemblies. lt includes a high-speed asynchronous data transfer bus allowing masters to direct the transfer of binary data to and from slaves according to 4 kinds of cycles: address-only, single-transfer, block-transfer and interrupt-acknowledge cycles. It also includes an arbitration bus enabling arbiter modules and/or requester modules to coordinate the use of the data-transfer bus according to two arbitration methods (series or parallel). Note: -For the price of this publication, please consult the ISO/IEC price-code list.