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Standard Guide for the Measurement of Single Event Phenomena (SEP) Induced by Heavy Ion Irradiation of Semiconductor Devices 半导体器件的重离子辐照引起的单事件现象(SEP)测量的标准指南
发布日期: 2024-05-01
1.1 本指南定义了测试集成电路和其他设备对原子序数重离子辐照引起的单事件现象(SEP)影响的要求和程序 Z ≥ 2.本描述特别排除了中子、质子和其他较轻粒子的影响,这些粒子可能通过不同的机制(例如电离或位移损伤)诱导SEP。SEP包括由单个离子撞击引起的任何扰乱表现,包括软错误(一个或多个同时可逆的位翻转)、硬错误(不可逆的位反转)、闩锁(持续高导通状态)、组合器件中引起的瞬态(可能在附近电路中引入软错误)、功率场效应晶体管(FET)烧坏- 以及闸门破裂。这种测试可能被认为是破坏性的,因为它通常涉及在辐照前移除设备盖子。位翻转通常与数字器件相关,锁存通常局限于体互补金属氧化物半导体(CMOS)器件,但在组合逻辑可编程只读存储器(PROM)和某些可能对重离子诱导的电荷瞬态做出响应的线性器件中也观察到重离子诱导SEP。功率晶体管可通过MIL STD 750的方法1080中规定的程序进行测试。 1.2 此处描述的程序可用于模拟和预测自然空间环境中产生的SEP,包括银河系宇宙射线、行星捕获离子、日冕物质抛射(CME)和太阳耀斑。 然而,这些技术并不能模拟重离子束与核的相互作用效应。测试的最终产物是SEP横截面(每单位注量的扰动/事件数)与离子LET(沿离子穿过半导体的路径沉积的线性能量转移或电离)的函数图。该数据可以与预期系统的重离子环境相结合,以估计操作期间的系统扰动率。 1.3 尽管质子会导致SEP,但它们不包括在本指南中。正在考虑一个单独的指南来解决质子诱导的SEP。 1.4 以国际单位制表示的数值应视为标准。 本标准不包括其他计量单位。 1.5 本标准并不旨在解决与其使用相关的所有安全问题(如有)。本标准的使用者有责任在使用前制定适当的安全、健康和环境实践,并确定监管限制的适用性。 1.6 本国际标准是根据世界贸易组织技术性贸易壁垒委员会发布的《关于制定国际标准、指南和建议的原则的决定》中确立的国际公认的标准化原则制定的。 ====意义和用途====== 5.1 许多现代集成电路、功率晶体管和其他设备在星际空间、卫星轨道或短暂穿过被捕获的辐射带时暴露于宇宙射线时会经历SEP。为了建立适当的技术来对抗所提出的系统中这种混乱的影响,能够预测特定环境的SEP速率是至关重要的。随着技术向更高密度的集成电路发展,这个问题可能会变得更加严重。 5.2 本指南旨在帮助实验者进行地面测试,以产生能够进行SEP预测的数据。
1.1 This guide defines the requirements and procedures for testing integrated circuits and other devices for the effects of single event phenomena (SEP) induced by irradiation with heavy ions having an atomic number Z ≥ 2. This description specifically excludes the effects of neutrons, protons, and other lighter particles that may induce SEP via different mechanisms, for example, ionization or displacement damage. SEP includes any manifestation of upset induced by a single ion strike, including soft errors (one or more simultaneous reversible bit flips), hard errors (irreversible bit flips), latchup (persistent high conducting state), transients induced in combinatorial devices which may introduce a soft error in nearby circuits, power field effect transistor (FET) burn-out, and gate rupture. This test may be considered to be destructive because it often involves the removal of device lids prior to irradiation. Bit flips are usually associated with digital devices and latchup is usually confined to bulk complementary metal oxide semiconductor (CMOS) devices, but heavy ion induced SEP is also observed in combinatorial logic programmable read-only memory (PROMs), and certain linear devices that may respond to a heavy ion induced charge transient. Power transistors may be tested by the procedure called out in Method 1080 of MIL STD 750. 1.2 The procedures described here can be used to simulate and predict SEP arising from the natural space environment, including galactic cosmic rays, planetary trapped ions, coronal mass ejections (CMEs), and solar flares. The techniques do not, however, simulate heavy ion beam nuclear interaction effects. The end product of the test is a plot of the SEP cross section (the number of upsets/events per unit fluence) as a function of ion LET (linear energy transfer or ionization deposited along the ion's path through the semiconductor). This data can be combined with an expected system's heavy ion environment to estimate a system upset rate during operation. 1.3 Although protons can cause SEP, they are not included in this guide. A separate guide addressing proton induced SEP is being considered. 1.4 The values stated in SI units are to be regarded as standard. No other units of measurement are included in this standard. 1.5 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety, health, and environmental practices and determine the applicability of regulatory limitations prior to use. 1.6 This international standard was developed in accordance with internationally recognized principles on standardization established in the Decision on Principles for the Development of International Standards, Guides and Recommendations issued by the World Trade Organization Technical Barriers to Trade (TBT) Committee. ====== Significance And Use ====== 5.1 Many modern integrated circuits, power transistors, and other devices experience SEP when exposed to cosmic rays in interplanetary space, in satellite orbits, or during a short passage through trapped radiation belts. It is essential to be able to predict the SEP rate for a specific environment in order to establish proper techniques to counter the effects of such upsets in proposed systems. As the technology moves toward higher density ICs, the problem is likely to become even more acute. 5.2 This guide is intended to assist experimenters in performing ground tests to yield data enabling SEP predictions to be made.
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