本出版物包含一组经常推荐和接受的JEDEC可靠性压力测试。这些测试用于鉴定新的和改进的技术/工艺/产品系列，以及单个固态表面贴装产品，尤其是无铅芯片载体、球栅阵列（BGA）封装、直接芯片连接芯片和带有暴露焊盘的封装，这些焊盘连接到PWB上是出于热考虑。组件级测试可能不是设备鉴定的先决条件；然而，如果装配条件对部件的影响未知，则该部件可能存在在部件级测试中不明显的可靠性问题。因此，建议进行装配级测试，以确定该部件是否因装配到PWB而产生任何不利影响。

This publication contains a set of frequently recommended and accepted JEDEC reliability stress tests. These tests are used for qualifying new and modified technology/ process/ product families, as well as individual solid state surface-mount products, in particular leadless chip carriers, ball grid array (BGA) packages, direct chip attach die and packages with exposed pads that are attached to the PWB for thermal considerations. Assembly level testing may not be a prerequisite for device qualification; however, if the effect of assembly conditions on the component is not known, there could be reliability concerns for that component that are not evident in component level testing. As such, it is recommended that assembly level testing be performed to determine if there are any adverse effects on that component due to its assembly to a PWB.