-活跃。 本标准代表了之前两个标准的合并:IEEE Std 1364？2005 Verilog硬件描述语言（HDL）和IEEE Std 1800-2005 SystemVerilog统一硬件设计、规范和验证语言。2005 SystemVerilog标准定义了对2005 Verilog标准的扩展。这两个标准旨在作为一种语言使用。将基本Verilog语言和SystemVerilog扩展合并到一个标准中，为用户提供了单个文档中有关语法和语义的所有信息。

Adoption Standard - Active. This standard represents a merger of two previous standards: IEEE Std 1364-2005 Verilog hardware description language (HDL) and IEEE Std 1800-2005 SystemVerilog unified hardware design, specification, and verification language. The 2005 SystemVerilog standard defines extensions to the 2005 Verilog standard. These two standards were designed to be used as one language. Merging the base Verilog language and the SystemVerilog extensions into a single standard provides users with all information regarding syntax and semantics in a single document.