本标准定义了宽I/O 2（WideIO2），包括特性、功能、AC和DC特性、封装和微柱信号分配。本标准的目的是定义符合JEDEC的8 Gb至32 Gb SDRAM设备的最低要求，该设备具有4或8个64位宽通道，使用直接芯片间连接方法，用于1至4个内存设备和控制器/缓冲设备。WideIO2体系结构是WIO体系结构的一种演变，能够随容量扩展带宽。

This standard defines Wide I/O 2 (WideIO2), including features, functionality, AC and DC characteristics, packages, and micropillar signal assignments. The purpose of this standard is to define the minimum set of requirements for JEDEC compliant, 8 Gb through 32 Gb SDRAM devices with 4 or 8 64-bit wide channels using direct chip-to-chip attach methods for between 1 and 4 memory devices and a controller/buffer device. The WideIO2 architecture is an evolution of the WIO architecture to enable bandwidth scaling with capacity.