IEC 61523-1:20 23专注于集成电路设计的延迟和功率计算，支持逻辑行为和信号完整性建模。 本文件涵盖的标准规范如下: -用于时序和功率建模的描述语言，称为“延迟计算语言”(DCL) -软件程序接口(PI)，用于EDA应用程序和DCL描述的编译库之间的通信 -用于关于芯片设计的寄生信息的标准文件交换格式:标准寄生交换格式(SPEF) -信息丰富的用法示例 -信息说明。 这是IEC/IEEE双标识标准。

IEC 61523-1:2023 focuses on delay and power calculation for integrated circuit design with support for modeling logical behavior and signal integrity.
The standard specifications covered in this document are as follows:
- Description language for timing and power modeling, called the “delay calculation language” (DCL)
- Software procedural interface (PI) for communications between EDA applications and compiled libraries of DCL descriptions
- Standard file exchange format for parasitic information about the chip design: Standard Parasitic Exchange Format (SPEF)
- Informative usage examples
- Informative notes.
This is an IEC/IEEE dual logo standard.