本标准规定了一种构造两级低密度奇偶校验（LDPC）码并将其用作非易失性存储器（NVM）中的纠错编码（ECC）方案的方法。文中给出了编码和解码方法，以及对内存和整个系统延迟的影响。给出了两级码构造方案与传统一级码构造方案的比较仿真结果，以及几种LDPC码速率和码长的奇偶校验矩阵。

This standard specifies a method to construct two-level low-density parity-check (LDPC) codes and to utilize them as the error correction coding (ECC) scheme in non-volatile memories (NVM). The encoding and decoding methods as well as the implications on memory and overall system latency are presented. The simulation results comparing the two-level code construction scheme and the traditional one-level scheme, as well as the parity check matrices for several LDPC code rates and lengths are provided.