本文件提供了正确描述CMOS和BiCMOS集成电路工艺或具有类似横向PNPN拓扑布局特性的其他工艺中闭锁行为所需的布局和测试方法的建议。

This document provides recommendations for the layout and test methods required to properly characterize the latchup behavior in CMOS and BiCMOS integrated-circuit processes or other processes that have similar lateral PNPN topographical layout characteristics.