ISO/TR 24119:2015阐明并解释了在多个无电势触点（B1至Bn）联锁装置串联至一个进行诊断的逻辑单元（K）的应用中的故障屏蔽原理（见图1至图7）。它还提供了如何估计故障掩蔽概率和相关联锁设备的最大直流电的指南。本技术报告仅涵盖两个通道均为物理串行连接的联锁设备。

ISO/TR 24119:2015 illustrates and explains principles of fault masking in applications where multiple interlocking devices with potential free contacts (B1 to Bn) are connected in series to one logic unit (K) which does the diagnostics (see Figures 1 to 7). It further provides a guide how to estimate the probability of fault masking and the maximum DC for the involved interlocking devices. This Technical Report only covers interlocking devices in which both channels are physical serial connections.