本标准定义了一种低成本的方法，用于测试离散、复杂存储器集成电路（IC）的互连，其中没有用于测试的额外引脚，且无法实现边界扫描（IEEE Std 1149.1）。本标准描述了兼容IC中测试逻辑和测试模式访问/退出方法的实施规则。本标准仅限于实施的行为描述，不包括测试逻辑或测试模式控制电路的技术设计。

This standard defines a low-cost method for testing the interconnection of discrete, complex memory integrated circuits (ICs) where additional pins for testing are not available and implementing boundary scan (IEEE Std 1149.1)1 is not feasible. This standard describes the implementation rules for the test logic and test mode access/exit methods in compliant ICs. The standard is limited to the behavioral description of the implementation and will not include the technical design for the test logic or test mode control circuitry.