本标准描述了为32位传输、多处理器操作和简单性而优化的计算机背板总线。简而言之，这是一个同步（10 MHz）、多路复用、多主总线，提供了严格公平的仲裁机制。唯一的总线传输是对单个32位地址空间的读写（以及每个总线的块传输版本）。地理插槽寻址和非人工链仲裁方案通过消除开关和跳线，简化了系统配置。这种极简主义的方法产生了一种概念上简单的总线，其引脚数很小（51条活动信号线）。图显示了典型NuBus系统的主要元素。

This standard describes a computer backplane bus optimized for 32-bit transfers, multiprocessor operations, and simplicity. In brief, this is a synchronous (10 MHz), multiplexed, multimaster bus that provides a strictly fair arbitration mechanism. The only bus transfers are read and write (and block transfer versions of each of these) to a single 32-bit address space. Geographic slot addressing and nondaisy-chain arbitration scheme make system configuration simpler by eliminating switches and jumpers. This minimalist approach results in a conceptually straightforward bus with a small pin count (51 active signal lines). Figure shows the major elements of a typical NuBus system.