定义一个高带宽接口，允许访问动态内存芯片中已有的大内部带宽。目标是通过使用SCI协议的子集来提高性能并降低内存系统的复杂性。将考虑分层存储系统，从多级缓存到主存储系统。接口规范将适用于单个内存芯片及其控制器。该接口应适用于满足near要求的商品部件- 未来（3-5年）和后续几代计算机系统。

Define a high-bandwidth interface that will permit access to the large internal bandwidth already available in dynamic memory chips. The goal is to increase the performance and reduce the complexity of memory systems by using a subset of SCI protocols. Hierarchical memory systems will be considered, from multi-level caches to main-memory systems. The interface specification will apply to individual memory chips as well as their controllers. The interface should be applicable to commodity parts that will fulfilll the requirements of near-future (3-5 years) and subsequent generations of computor systems.