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STANDARD DESCRIPTION OF LOW-VOLTAGE TTL-COMPATIBLE, 5 V TOLERANT CMOS LOGIC DEVICES 低压TTL兼容、5V容限CMOS逻辑器件的标准描述
发布日期: 1996-06-01
本标准概述了逻辑产品的标准直流规范、测试条件和测试负载,这些逻辑产品的设计允许输入和输出电压超过设备电源。更具体地说,这标准化了从“低压”(2.7 V到3.6 V)电源运行的5 V容限逻辑电路。符合本标准的产品可用于LVCMOS/LVTTL和5V TTL总线之间的有效接口,从而弥合低压和5V TTL总线之间的间隙。
This standard outlines the standard dc specifications, test conditions, and test loading for logic products that are designed to tolerate input and output voltages which exceed the device's power supply. More specifically this standardizes 5 V - tolerant logic prducts that run from 'low voltage' (2.7 V to 3.6 V) power supplies. Products that meet this standard can be used to effectively interface between LVCMOS/LVTTL and 5 V TTL buses, bridging the gap between low-voltage and 5 V TTL busses.
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