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现行 JEDEC JESD51-8
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INTEGRATED CIRCUIT THERMAL TEST METHOD ENVIRONMENTAL CONDITIONS - JUNCTION-TO-BOARD 集成电路热试验方法环境条件.接线板
发布日期: 1999-10-01
本规范应与概述文件JESD51、组件封装(单个半导体器件)的热测量方法[1]以及JESD51-1中描述的电气测试程序结合使用,“集成电路热测量方法(单半导体器件)”[2.本文件中描述的环境条件专门用于测试安装在带有两个内部铜平面的标准测试板上的集成电路器件[3]。 本标准不适用于因热增强而导致印制板热流路径不对称的封装,如熔合引线(引线连接到芯片垫)或封装一侧有暴露热段塞的电源型封装。
This specification should be used in conjunction with the overview document JESD51, Methodology for the Thermal Measurement of Component Packages (Single Semiconductor Device) [1] and the electrical test procedures described in JESD51-1, 'Integrated Circuit Thermal Measurement Method (Single Semiconductor Device' [2. The environmental conditions described in this document are specifically designed for testing of integrated circuit devices that are mounted on standard test boards with two internal copper planes [3]. This standard is not applicable to packages that have asymmetric heat flow paths to the printed board caused by such thermal enhancements as fused leads (leads connected to the die pad) or power style packages with the exposed heat slug on one side of the package.
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发布单位或类别: 美国-JEDEC固态技术协会
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