首页 馆藏资源 舆情信息 标准服务 科研活动 关于我们
现行 IEEE/IEC 62530-2007
到馆提醒
收藏跟踪
购买正版
IEC 62530 Ed. 1 (IEEE Std 1800(TM)-2005): Standard for SystemVerilog - Unified Hardware Design, Specification, and Verification Language IEC 62530第1版(IEEE Std 1800(TM)-2005):SystemVerilog标准——统一硬件设计、规范和验证语言
发布日期: 2007-12-09
本标准规定了更高抽象级别的扩展,用于使用 Verilog?硬件描述语言(HDL)。这些新增功能将Verilog扩展到了系统空间和 验证空间。SystemVerilog是建立在IEEE Std 1364?1之上的Verilog HDL。这 标准包括设计规范方法、嵌入式断言语言、测试平台语言 包括覆盖和断言应用程序编程接口(API)和直接编程 接口(DPI)。 在本标准中,以下条款适用: Verilog指的是Verilog HDL的IEEE标准1364。 Verilog-2001是指Verilog HDL的IEEE Std 1364-2001[B4]2。 Verilog-1995是指Verilog HDL的IEEE Std 1364-1995[B3]。 SystemVerilog是指本规范中定义的Verilog标准(IEEE Std 1364)的扩展 标准 SystemVerilog向Verilog添加了扩展和新结构,包括以下内容: 对数据类型的扩展,以更好地封装和压缩代码,并实现更紧密的 规格 C数据类型:int、typedef、struct、union、enum 其他数据类型:有界队列、逻辑(0,1,X,Z)和位(0,1)、为安全起见标记的联合 动态数据类型:字符串、类、动态队列、动态数组、关联数组 包括自动内存管理,让用户免于释放问题 动态铸造和钻头流铸造 ?基于每个变量实例的自动/静态规范 ?扩展运算符,便于简洁描述 疯狂的平等和不平等 内置的扩展语言的方法 操作员超载 流媒体运营商 设定会员资格 扩展程序声明 ?选择语句上的模式匹配,用于标记的联合 增强的循环语句加上foreach语句 类C跳转语句:返回、中断、继续 ?模拟结束时执行的最终块(与初始块相反) 扩展事件控制和序列事件 ?强化过程控制 ?对always块的扩展,包括合成一致性模拟语义 扩展到forka?连接到模型管线并增强过程控制 细粒度过程控制 ?增强的任务和功能 类C空函数 通过参考 默认参数 按名称绑定的参数 可选参数 ?DPI的导入/导出功能 类:提供抽象、封装和安全指针的面向对象机制 能力 ?具有随机约束的自动化测试台支持 进程间通信同步 信号灯 邮箱 事件扩展、事件变量和事件顺序 ?调度语义的澄清和扩展 基于周期的功能:计时块和基于周期的属性有助于减少开发, 简化可维护性,提高可重用性 ?基于周期的信号驱动和采样 同步采样
This standard specifies extensions for a higher level of abstraction for modeling and verification with the Verilog® hardware description language (HDL). These additions extend Verilog into the systems space and the verification space. SystemVerilog is built on top of IEEE Std 1364™1 for the Verilog HDL. This standard includes design specification methods, embedded assertions language, testbench language including coverage and assertions application programming interface (API), and a direct programming interface (DPI). Throughout this standard, the following terms apply: — Verilog refers to IEEE Std 1364 for the Verilog HDL. — Verilog-2001 refers to IEEE Std 1364-2001 [B4]2 for the Verilog HDL. — Verilog-1995 refers to IEEE Std 1364-1995 [B3] for the Verilog HDL. — SystemVerilog refers to the extensions to the Verilog standard (IEEE Std 1364) as defined in this standard. SystemVerilog adds extended and new constructs to Verilog, including the following: — Extensions to data types for better encapsulation and compactness of code and for tighter specification — C data types: int, typedef, struct, union, enum — Other data types: bounded queues, logic (0, 1, X, Z) and bit (0, 1), tagged unions for safety — Dynamic data types: string, classes, dynamic queues, dynamic arrays, associative arrays including automatic memory management freeing users from deallocation issues — Dynamic casting and bit-stream casting — Automatic/static specification on a per-variable-instance basis — Extended operators for concise description — Wild equality and inequality — Built-in methods to extend the language — Operator overloading — Streaming operators — Set membership — Extended procedural statements — Pattern matching on selection statements for use with tagged unions — Enhanced loop statements plus the foreach statement — C-like jump statements: return, break, continue — final blocks that execute at the end of simulation (inverse of initial) — Extended event control and sequence events — Enhanced process control — Extensions to always blocks to include synthesis consistent simulation semantics — Extensions to fork…join to model pipelines and for enhanced process control — Fine-grain process control — Enhanced tasks and functions — C-like void functions — Pass by reference — Default arguments — Argument binding by name — Optional arguments — Import/export functions for DPI — Classes: object-oriented mechanism that provides abstraction, encapsulation, and safe pointer capabilities — Automated testbench support with random constraints — Interprocess communication synchronization — Semaphores — Mailboxes — Event extensions, event variables, and event sequencing — Clarification and extension of the scheduling semantics — Cycle-based functionality: clocking blocks and cycle-based attributes that help reduce development, ease maintainability, and promote reusability — Cycle-based signal drives and samples — Synchronous samples
分类信息
关联关系
研制信息
相似标准/计划/法规