结构在STIL中定义，以支持用作半导体模拟刺激，包括 （1） 将信号名称映射到等效设计参考，（2）扫描和内置自检之间的接口 （BIST）和逻辑模拟，（3）表示模式中未解析状态的数据类型，（4）并行或 不同设计块上的异步模式执行，以及（5）基于表达式的条件执行 模式构造的定义。 结构在STIL中定义，以支持设计子块的测试模式定义4 （即嵌入式内核），以便这些测试可以整合到完整的更高级别设备测试中。 在STIL中定义了结构，将设备测试环境中的故障信息与原始环境联系起来 刺激和设计数据元素。 4附录O总结了本文件中用于子块模式定义的语法。

Structures are defined in STIL to support usage as semiconductor simulation stimulus, including (1) mapping signal names to equivalent design references, (2) interface between scan and built-in self test (BIST) and the logic simulation, (3) data types to represent unresolved states in a pattern, (4) parallel or asynchronous pattern execution on different design blocks, and (5) expression-based conditional execution of pattern constructs. Structures are defined in STIL to support the definition of test patterns for sub-blocks of a design4 (i.e., embedded cores) such that these tests can be incorporated into a complete higher level device test. Structures are defined in STIL to relate fail information from device testing environments back to original stimulus and design data elements. 4 Syntax in this document that is used in the definition of patterns for sub-blocks is summarized in Annex O.