计算机系统中最重要的元素之一是为所有硬件组件提供接口的总线结构。该总线结构包含必要的信号，以允许各种系统组件相互作用。它允许内存和I/O数据传输、直接内存访问、中断生成等。 本标准详细描述了构成IEEE Std 796总线的所有元件和功能。 总线支持两个独立的地址空间:内存和I/O。在内存周期内，总线允许使用24位寻址，直接寻址能力高达16兆字节。在I/O总线周期中，总线允许使用16个端口寻址多达64 KB的I/O端口- 位寻址。内存和I/O周期可支持8位或16位数据传输。 总线结构建立在主从概念之上，系统中的主设备在解码其地址时控制总线和从设备，并根据主设备提供的命令进行操作。主设备和从设备之间的这种握手（主从关系）允许通过总线连接不同速度的模块。它还允许数据传输速率高达每秒500万次（字节或字）。 总线的另一个重要特性是能够连接多个主模块以进行多处理配置。 总线提供控制信号，以串行或并行优先方式连接多个主机。通过这两种安排中的任何一种，多个主机可以共享总线资源。 本标准适用于评估或设计与IEEE Std 796系统总线结构兼容的产品的用户。为此，我们详细介绍了必要的信号定义、定时和电气规范。 本标准仅涉及微机设备的接口特性，不涉及模块的设计规范、性能要求和安全要求。 在本标准中，术语系统表示字节或字接口系统，通常包括所有电路、连接器和控制协议，以实现设备之间明确的数据传输。 术语设备或模块表示连接到接口系统的任何产品，该产品通过总线传输信息，并且符合接口系统定义。

One of the most important elements in a computer system is the bus structure that supplies the interface for all the hardware components. This bus structure contains the necessary signals to allow the various system components to interact with each other. It allows memory and I/O data transfers, direct memory accesses, generation of interrupts, etc. This standard provides a detailed description of all the elements and features that make up the IEEE Std 796 bus. The bus supports two independent address spaces: memory and I/O. During memory cycles, the bus allows direct addressability of up to 16 megabytes using 24-bit addressing. During I/O bus cycles, the bus allows addressing of up to 64 kilobyte I/O ports using 16-bit addressing. Memory and I/O cycles can support 8-bit or 16-bit data transfers. The bus structure is built upon the masterslave concept where the master device in the system takes control of the bus and the slave device, upon decoding its address, and acts upon the command provided by the master. This handshake (master-slave relationship) between the master and slave devices allows modules of different speeds to be interface by way of the bus. It also allows data rates up to five million transfers per second (bytes or words) to take place across the bus. Anotherre important feature of the bus is the ability to connect multiple master modules for multiprocessing configurations. The bus provides control signals for connecting multiple masters in either a serial or parallel priority fashion. With either of these two arrangements, more than one master may share bus resources. This standard has been prepared for those users who evaluate or design products that will be compatible with the IEEE Std 796 system bus structure. To this end, the necessary signal definitions and timing and electrical specifications have been covered in detail. This standard deals only with the interface characteristics of microcomputer devices, not with design specifications, performance requirements, and safety requirements of modules. Throughout this standard, the term system denotes the byte or word interface system that, in general, includes all the circuits, connectors, and control protocol to effect unambiguous data transfer between devices. The term device or module denotes any product connected to the interface system that communicates information by way of the bus, and that conforms to the interface system definition.