1450测试接口（STIL）和核心测试语言包提供了数字测试生成工具和测试设备之间的接口，以及数字测试生成工具和测试设备之间的接口。它在STIL中定义了用于指定被测设备直流条件的结构。STIL环境支持将独立于测试人员的测试程序传输到特定的ATE系统。 核心测试语言（CTL）是为片上系统流（或SoC流）创建的语言，其中一个组创建的设计被重用为另一个组创建的设计的子设计。它定义了如何将必要的信息从扫描插入传递到模式生成，以及从模式生成传递到诊断，从而使不同的工具供应商可以独立于on应用于每个步骤- 使用芯片扫描压缩逻辑。它定义的语言结构足以表示内存核心的上下文，以及将该内存核心集成到片上系统流（SoC）中的上下文。

The 1450 test interface (STIL) and Core Test language bundle provides an interface between digital test generation tools and test equipment and interface between digital test generation tools and test equipment. It defines structures in STIL for specifying the DC conditions for a device under test. The STIL environment supports transferring tester-independent test programs to a specific ATE system. The Core Test Language (CTL) is a language created for a System-on-Chip flow (or SoC flow), where a design created by one group is reused as a sub-design of a design created by another group. It defines how the necessary information is passed from scan insertion to pattern generation and from pattern generation to diagnosis such that different tool vendors could be used for each step independent of on-chip scan compression logic used. It defines language constructs sufficient to represent the context of a memory core and of the integration of that memory core into an System-on-Chip flow (SoC).