定义STIL中的结构，以支持将其用作半导体模拟刺激；包括:1）将信号名称映射到等效设计参考，2）扫描和BIST之间的接口，以及逻辑模拟，3）表示模式中未解析状态的数据类型，4）不同设计块上的并行或异步模式执行，以及5）基于表达式的模式构造条件执行。在STIL中定义结构，以支持设计子块（即嵌入式内核）测试模式的定义，从而将这些测试纳入完整的更高级别设备测试。在STIL中定义结构，将设备测试环境中的故障信息与原始刺激和设计数据元素联系起来。

Define structures in STIL to support usage as semiconductor simulation stimulus; including: 1) mapping signal names to equivalent design references, 2) interface between Scan and BIST, and the logic simulation, 3) data types to represent unresolved states in a pattern, 4) parallel or asynchronous pattern execution on different design blocks, and 5) expression-based conditional execution of pattern constructs. Define structures in STIL to support the definition of test patterns for sub-blocks of a design (i.e., embedded cores) such that these tests can be incorporated into a complete higher-level device test. Define structures in STIL to relate fail information from device testing environments back to original stimulus and design data elements.