IEC 60191-6:20 09给出了制备表面贴装半导体器件轮廓图的一般规则。它补充了IEC 60191-1和IEC 60191-3。它涵盖了引线数大于或等于8的所有表面贴装器件分立半导体，以及IEC 60191-4第3条中归类为表格E的集成电路。IEC 60191-6的第三版取消并取代了2004年发布的第二版，构成了技术修订。与上一版相比，此版本包含以下重大变更: a)修改范围以涵盖引线数大于或等于8的所有表面贴装器件分立半导体； b)对若干页进行编辑修改；和 c)球栅阵列封装（BGA）的技术修订，特别是其几何绘图格式。（由于修改了绘图格式，两种类型的BGA将统一为一种类型。

IEC 60191-6:2009 gives general rules for the preparation of outline drawings of surface-mounted semiconductor devices. It supplements IEC 60191-1 and IEC 60191-3. It covers all surface-mounted devices discrete semiconductors with lead count of greater or equal to 8, as well as integrated circuits classified as form E in Clause 3 of IEC 60191-4. This third edition of IEC 60191-6 cancels and replaces the second edition, published in 2004 and constitutes a technical revision. This edition includes the following significant changes with respect to the previous edition:
a) scope is modified to cover all surface-mounted devices discrete semiconductors with lead count of greater or equal to 8;
b) editorial modifications on several pages; and
c) technical revision to ball grid array package (BGA) especially its geometrical drawing format. (two types of BGA would unify as one type as a result of revising drawing format.